The integration density of an integration circuit has been remarkably improved each year due to the miniaturization of a transistor and the like. In case of an integration circuit adopting a MOSFET, such miniaturization of the transistor can promote the miniaturization of components of the transistor according to a proportional reduction rule. However, it is known that a short channel effect of the transistor may occur as the miniaturization is progressed.
For example, if a channel length is shortened according to the proportional reduction rule, a threshold value of the transistor fluctuates greatly due to a minute change in the channel length, and also, a sub-threshold characteristic is deteriorated. Accordingly, there may occur problems such as an excessive increase of the threshold value for sufficiently restraining a standby current.
In addition, since a voltage applied to the transistor is not subject to the proportional reduction rule, an electrical characteristic required for a gate insulating film could not be obtained by using a silicon oxide film, so that a high-k dielectric film is used as the gate insulating film instead of the silicon oxide film. Here, the high-k dielectric film refers to a film having a dielectric constant greater than that of the silicon oxide film. The high-k dielectric film includes a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a tantalum oxide film, a hafnium oxide film, a zirconium oxide film and the like.
Moreover, the threshold value of the transistor is generally controlled by performing an ion implantation on a semiconductor substrate, or by using a work function difference between a gate electrode and the semiconductor substrate. In addition, a fixed charge is provided in the gate insulating film or an interface between the semiconductor substrate and the gate insulating film to control the threshold value of the transistor. When controlling the threshold value of the transistor by performing only the ion implantation, if the channel length becomes 0.2 microns or less, the threshold value considerably becomes nonuniform due to a statistical nonuniformity of the implanted ion. Therefore, it is desirable to use a combination of the above-described technologies for controlling the threshold value in a micro-MOSFET.
For instance, a pMOS having a structure shown in FIGS. 5a and 5b is described in Non-patent Document 1 or 2. In this pMOS, a film made of hafnium oxide (HfO2) and aluminum oxide (Al2O3) is used as the gate insulating film, and the threshold value is controlled by using a gate structure having a stack of nickel silicided (Ni—FUSI) gate electrode /Al2O3/HfO2/Si. FIG. 5c shows a characteristic of a flat band voltage with respect to an equivalent oxide thickness (EOT), for each gate insulating film. The gate insulating films used here are Al2O3/SiO2, Hf(20%)Al(80%)Ox/SiO2, Hf(50%)Al(50%)Ox/SiO2, Hf(80%)Al(20%)Ox/SiO2, HfO2/SiO2, and SiO2 as a reference.
In these cases, a Vfb value increases as Al concentration increases, but this value is not appropriate for a pMOSFET of a CMOS circuit. In addition, in case of Al2O3, an effective work function equivalent value reaches only 4.8 eV, and particularly, in case of HfO2, the value falls down to 4.6 eV. Thus, in case of using a high-k dielectric film starting with a HfO2 film as the gate insulating film of the pMOSFET, it is difficult for the threshold value to be lowered (as an absolute value).
In addition, Patent Document 1 discloses a MOS transistor capable of stabilizing a threshold voltage and a flat band voltage by installing an intermediate layer, such as aluminum nitride or aluminum oxynitride, between a gate electrode containing silicon and a high-k gate dielectric material such as hafnium oxide, hafnium silicate or hafnium silicon oxynitride.
Further, Patent Document 2 discloses a MIS field-effect transistor having a laminated gate insulating film made of a hafnium aluminum oxide layer and a silicon oxynitride interface layer, capable of suppressing instability of a threshold voltage by removing a hysteresis characteristic of each layer.
Furthermore, Patent Document 3 discloses a MIS semiconductor device employing a laminated gate insulating film made of an aluminum oxide layer and a silicon oxide layer of zirconium or hafnium installed on a conductive channel.
Furthermore, Patent Document 4 discloses an NMOSFET provided with a gate insulating film, which is made of a silicon oxide film and a hafnium silicate film, and a gate electrode having an N-type polysilicon film formed on the gate insulating film. Also, disclosed is a PMOSFET provided with a gate insulating film, which is made of a silicon oxide film, a hafnium silicate film and an aluminum oxide film, and a gate electrode having a P-type polysilicon film formed on the gate insulating film.
Furthermore, Patent Document 5 discloses a method of controlling a threshold voltage by implanting Be, Al, Cr, Co, Cu, Ge, Au, In, Ir, Fe, Pb, Mn, Mo, Ni, Pd, Rh, Si, Ag, Ta, Tl, Ti, W, V or Zr into an insulating film formed on a semiconductor substrate.
However, the threshold voltage is not sufficiently controlled only through a combination of the above-described conventional techniques. For example, in case of the P-channel MOSFET employing the hafnium oxide film having a high dielectric constant as the gate insulating film, the threshold voltage shows a value equal to or less than (more than at absolute value) what is required for a circuit design. In Non-patent Document 1 or 2, the HfO2 film is provided with Al2O3 to control the threshold voltage by using a work function difference, or a Vth of the pMOS is controlled by forming a gate structure to a stack structure of gate electrode/Al2O3/HfO2/Si. The threshold voltage (or flat band voltage) can be shifted about 0.2V in comparison with the case of the HfO2 film, but it does not meet the value required for the circuit design.
[Non-patent Document 1] M. Kadoshima et al., Symp. VLSI Tech. Dig., 2005, 70    [Non-patent Document 2] H. S. Jung et al., Symp. VLSI Tech. Dig., 2005, 232    [Patent Document 1] Japanese Patent Laid-open Application No. 2005-328059    [Patent Document 2] Japanese Patent Laid-open Application No. 2004-158498    [Patent Document 3] Japanese Patent Laid-open Application No. 2002-343965    [Patent Document 4] Japanese Patent Laid-open Application No. 2006-108439    [Patent Document 5] U.S. Pat. No. 4,297,782